Two design objectives for electronic power amplifier circuits are high efficiency and high power density. RF amplifiers of a type known as switching amplifiers provide both high efficiency and high power density by operating an active electronic device, such as a transistor, as a switch that is either fully on or fully off. Unfortunately, switching loss also increases as a function of switching frequency, resulting in lost power. Switching loss is attributable to practical limitations in the semiconductor devices that are used as switching elements in power conversion circuits. These limitations include non-zero switching time and non-zero device capacitance.
Soft switching amplifier circuits have been used in applications where high frequency power switching is required in conjunction with low power loss. As a practical matter, the power and frequency range of soft switching circuits is limited by the parasitic reactive impedances of semiconductor-based switching elements. In particular, in some classes of switching conversion circuit topologies, the aforementioned parasitic reactive impedances set a lower limit on power throughput for a given switching frequency and an upper limit on switching frequency for a given power level. Some of the topologies subject to this limitation include Class E, Class F, Class Φ, and their duals, inverses, and other derivative circuits. Unfortunately, this lower limit may be higher than the maximum power desired, or the frequency may be lower than desired, with the effect that it is not possible to simultaneously achieve high efficiency and high power density.
FIG. 1 is a block diagram showing a simplified prior art high frequency amplifier cell 20. Cell 20 accepts an input from a DC voltage source VG 10 supplying an input power PIN. The input impedance of cell 20 is ZIN. An AC signal S1 is produced by an AC signal source 11. Signal S1 has a frequency FS for controlling the modulation of the input power PIN. Typically, signal S1 is a low power signal. In response to signal S1, cell 20 provides an AC output signal POUT of much higher power than S1 to a load impedance ZL 49. Assuming that cell 20 is implemented using low-loss elements, PIN=POUT=P is a close approximation, where P=(VG2)/ZIN.
FIG. 2 is a more detailed block diagram of the prior art high frequency resonant power amplifier cell shown in FIG. 2. Cell 20 includes a first network 12, a second network 32, and an active switch 22. Active switch 22 is controlled by an AC signal S1 produced by an AC signal source 11. Signal S1 has a frequency FS. First network 12 has a first port 14 and a second port 16. Second network 32 has a first port 34 and a second port 36. First port 14 of first network 12 is operatively coupled to voltage source VG 10, and second port 36 of second network 32 is operatively coupled to load impedance ZL 49. Second port 16 of first network 12 is operatively coupled to first port 34 of second network 32. First network 12 functions as a DC feed network, feeding a DC voltage from voltage source VG 10 to second network 32. Second network 32 functions as an impedance matching network for matching the impedance of first network 12 and active switch 22 to load impedance ZL 49. Illustratively, first network 12 is implemented as a low-loss network of circuit elements for interfacing VG 10 with second network 32 and active switch 22 so as to permit soft switching of active switch 22. Illustratively, second network 32 is implemented as a low-loss impedance matching network of circuit elements selected so as to permit soft switching of active switch 22. In practice, it is sometimes possible to have the functions of networks 12 and 32 provided by a single network.
Active switch 22 is operatively coupled in shunt across second port 16 and first port 34. Active switch 22 includes a switching mechanism 24 which is turned on and off at input switching frequency FS provided by input signal S1. Switching mechanism 24 provides an inherent parasitic capacitance C1 represented schematically by a capacitor 26. More specifically, capacitor 26 is not present as a separate element, but rather exists as an integral part of active switch 22 along with switching mechanism 24. Typically, capacitor 26 represents the inherent parasitic output capacitance (C1) of a semiconductor device used to implement active switch 22. Illustratively, active switch 22 is implemented using a soft switching circuit capable of high frequency operation, such as a Class E circuit. Class E circuits utilize a soft switching technique termed zero-voltage switching (ZVS) to operate a semiconductor-based main power switch at near zero switching voltage for both turn-on and turn-off, resulting in very low switching losses. Other circuit classes such as F, Φ, and their derivatives are also capable of such operation.
If soft switching is to occur, the impedance Z1 of active switch mechanism 22 should fall within a predetermined range. Z1 is defined by a parallel combination of first port 34 of second network 32, second port 16 of first network 12, and the parasitic capacitance C1 of active switch 22 as represented by capacitor 26. If too much parasitic capacitance C1 is present, the maximum allowable switching frequency FS for a given power POUT is too low to achieve a desired power density while still maintaining soft switching. Under these circumstances, the existence of parasitic capacitance C1 across active switch 22 will not permit ZVS operation. More specifically, for a product of capacitance C1 and desired switching frequency FS, there is a lower limit Pmin on power throughput below which ZVS operation cannot be achieved. This lower limit is expressed mathematically as Pmin=KV2*(FS)*(C1) where K is a constant based upon the circuit topology of the power conversion circuit. As a practical matter, capacitance C1 can never be lower than the parasitic output capacitance of the device used to implement active switch 22, and this value of C1 thus defines lower limit Pmin.
If the required power throughput for a given system application is lower than lower limit Pmin, it is possible to reduce Pmin by lowering the switching frequency FS, or by not utilizing soft switching, but neither of these options may represent acceptable choices. Moreover, while there are a number of presently existing ZVS circuits which provide alternatives to Class E designs, such alternatives are nonetheless also limited in terms of the lowest achievable power throughput. These alternative circuits require additional components that may reduce efficiency and power density, such that the goals of high efficiency and high power density may not be achieved simultaneously.
In some cases, it may be possible to reduce lower limit Pmin by the addition of a shunt inductive reactance in parallel with active switch 22 and capacitor 26. The inductive reactance cancels all or some of the parasitic capacitance C1 at one frequency, thus permitting switching frequency FS to be increased. Accordingly, if cancellation of some or all of the capacitive reactance of capacitor 26 is desired, this may be accomplished by designing at least one of first network 12 or second network 32 to provide an appropriate inductive reactance.
There are practical difficulties associated with using an inductive reactance in a switching power conversion circuit so as to permit active switching. First, the amount of capacitive reactance that can be cancelled is an increasing function of the quality factor Q of the inductor or network used to provide the inductive reactance. Since realizable inductors have finite values of Q, only a finite amount of capacitive reactance can be cancelled. Second, the sensitivity of the resonant network formed by the parallel inductance in shunt with the parasitic output capacitance of the main power switch is an increasing function of the amount of capacitive reactance to be cancelled. Thus, as more capacitance is cancelled, the permissible variation in component values becomes smaller, and implementation becomes more difficult.
Parasitic capacitance C1 sets a lower limit on power throughput and an upper limit on switching frequency. In practice, the lower limit may be higher than the maximum power desired, or the switching frequency may be lower than desired, with the effect that it is not possible to simultaneously achieve high efficiency and high power density. What is needed, therefore, is a switching power amplifier circuit capable of simultaneously providing high power density and high efficiency.
It is well known that a high frequency amplifier can be used a part of a DC/DC converter, adding a rectifier onto the output of the amplifier to convert the AC output signal to a DC output signal of approximately the same power but having a voltage and a current that may be different than the input DC voltage and current. In particular, the use of switching amplifiers such as Class E, Class F, Class Φ, and their duals, inverses, and other derivative circuits allow a high-efficiency, high density DC/DC converter to be constructed. Accordingly, the background presented thus far also applies to DC/DC converters.